Analysis of delay caused by Resistive Bridging faults in Secured CMOS 45 nm Technology, Implemented in QDI GHANIA AIT ABDELMALEK, REZKI ZIANI and MOURAD LAGHROUCHE
نویسندگان
چکیده
The article focuses on the defects modeling of secured CMOS circuits, implemented in Quasi Delay Insensitive (QDI). We analyze the static and the dynamic behavior of resistive bridges as a function of its unpredictable resistance. SPICE simulations were performed for 45nm CMOS technology. Simulation results are given for the conditions of defect detection and for the delay induced by the resistive bridging faults. Key-Words: asynchronous circuits, SecLib, resistive bridging faults; small delay faults; fault models, testability, fault detcetion.
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